Electronic devices incorporating integrated circuits, such as application specific integrated circuits (ASICs), often employ power saving techniques to reduce power consumption and thereby achieve extended battery life. Small, portable devices such as mobile telephones and personal digital assistants (PDAs), for example, typically incorporate circuitry for implementing inactive modes to limit power consumption by logic circuitry. Inactive modes may include stand-by, low power and sleep modes.
Power dissipation in digital circuits, and more specifically in Complementary Metal Oxide Semiconductor (CMOS) circuits, is approximately proportional to the square of the supply voltage. Therefore, an effective way to achieve low-power performance is to scale down the supply voltage. CMOS circuits on ASICs are capable of operating at significantly reduced power levels. In order to avoid increases in propagation delay, however, the threshold voltage of the CMOS devices also is reduced.
The reduction in threshold voltage generally causes an increase in stand-by current due to changes in the sub-threshold leakage current of Metal Oxide Semiconductor (MOS) devices. The leakage current that flows through an “off” transistor tends to increase exponentially as the threshold voltage of a device is reduced. Therefore, electronic devices such as mobile telephones and PDAs that remain in an inactive mode for an extended period of time can exhibit significant leakage current, and cause undesirable drain on battery power during the inactive mode.
In order to reduce leakage current during stand-by modes, some ASICs include power switches (e.g., headswitches and/or footswitches) that are electrically connected between the logic gates of a CMOS circuit and the power bus VDD or ground bus VSS. A headswitch can be a PMOS transistor positioned between the local power bus routing of an ASIC core or block and the top-level power bus routing. A footswitch can be an NMOS transistor positioned between the local ground bus and the top-level ground bus. Generally, headswitches and footswitches are CMOS or other devices which disconnects power or ground potential to source of circuit under test or circuit being controlled. Power switches may be used herein to refer to either a headswitches or footswitches.
During an inactive mode (“sleep mode”), the power switches (e.g., headswitches and/or footswitches) are turned off to disconnect the logic gates from the power/ground supply and thereby “collapse” the voltage across the connected circuit. Because the headswitch or footswitch has a high threshold voltage, the amount of leakage current drawn from the power supply by the power switches (e.g., headswitches and/or footswitches) is substantially reduced relative to the leakage current that would otherwise flow through the logic gates. During an active or operation mode, the headswitches or footswitches are turned on to connect the power supply or ground, respectively, to the gates. Therefore, during an active mode, the logic gates are powered by substantially the same voltage as if they were directly connected to the power supply and ground.
An example directed to a conventional power switch implementation will now be described. FIG. 1 illustrates a conventional semiconductor device 100. The semiconductor device 100 includes at least one circuit 105 and a controller 110. The controller 110 determines whether footswitches (e.g., NMOS transistors) included in a power switch array or matrix 115 are turned “on” or “off”. In particular, the controller 110 is configured to receive an external signal indicating whether the circuit 105 is operating in an active mode, or alternatively whether the circuit 105 can enter or remain in an idle state or sleep mode. Based on the external signal, the controller 110 signals the switches (e.g., footswitches) of the power switch matrix 115 to be “on” or “off” (e.g., by applying a signal to a gate thereof). The power switch matrix 115 is connected between a local ground at the circuit 105 and a ground bus 120 that carries a ground voltage VSS. Also shown in FIG. 1 is a power bus 125 that provides a power voltage VDD to the circuit 105.
FIG. 2 illustrates a conventional headswitch configuration. The semiconductor device 200 includes at least one circuit 205 and a controller 210. The controller 210 determines whether the headswitches (e.g., PMOS transistors) included in a power switch array or matrix 215 are turned “on” or “off”. In particular, the controller 210 is configured to receive an external signal indicating whether the circuit 205 is operating in an active mode, or alternatively whether the circuit 205 can enter or remain in an idle state or steep mode. Based on the external signal, the controller 210 signals the headswitches of the power switch matrix 215 to be “on” or “off” (e.g., by applying a signal to a gate thereof). The power switch matrix 215 is connected between a local VDD at the circuit 205 and a power bus 225 that carries a supply voltage VDD. Also shown in FIG. 2 is a ground bus/VSS 220 coupled to circuit(s) 205.
As will be appreciated in view of the description given above with respect to FIGS. 1 and 2, the controller (110, 210) turns the switch matrix (115, 215) on or off based on a mode signal received from an external entity. However, a transition of multiple transistors that can collectively constitute the power switch matrix (115, 215) from a first state (e.g., off) to a second state (e.g., on) can potentially cause a significant inrush current to be induced in the respective semiconductor device (100, 200), which may cause damage or malfunctioning of the controlled circuit(s) (105, 205).